Invited Paper: Partial correctness of C-MOS switching circuits: an exercise in applied logic (at LICS 1988)

Authors: C. Anthony R. Hoare Michael J. C. Gordon

Abstract

The possibility of extending some of the logical methods that have been recommended for the design of software to the design of hardware, in particular, of synchronous switching circuits implemented in CMOS, is explored. The objective is to design networks that are known by construction. Things that can go wrong with circuits designed in this way are examined. The application of the techniques is discussed

BibTeX

  @InProceedings{HoareGordon-Partialcorrectnesso,
    author = 	 {C. Anthony R. Hoare and Michael J. C. Gordon},
    title = 	 {Partial correctness of C-MOS switching circuits: an exercise in applied logic },
    booktitle =  {Proceedings of the Third Annual IEEE Symposium on Logic in Computer Science (LICS 1988)},
    year =	 {1988},
    month =	 {July}, 
    pages =      {28--36},
    location =   {Edinburgh, Scotland, UK}, 
    note =       {Invited Talk},
    publisher =	 {IEEE Computer Society Press}
  }